FinFET with dielectric isolated channel

ABSTRACT

Embodiments of the present invention provide a fin type field effect transistor (FinFET) and methods of fabrication. A punchthrough stopper region is formed on a semiconductor substrate. An insulator layer, such as silicon oxide, is formed on the punchthrough stopper. Fins and gates are formed on the insulator layer. The insulator layer is then removed from under the fins, exposing the punchthrough stopper. An epitaxial semiconductor region is grown from the punchthrough stopper to envelop the fins, while the insulator layer remains under the gate. By growing the fin merge epitaxial region mainly from the punchthrough stopper, which is part of the semiconductor substrate, it provides a higher growth rate then when growing from the fins. The higher growth rate provides better epitaxial quality and dopant distribution.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a Continuation of U.S. patent applicationSer. No. 14/248,455 filed on Apr. 9, 2014.

FIELD OF THE INVENTION

The present invention relates generally to semiconductor fabrication,and more particularly, to a fin type field effect transistor (FinFET)and methods of fabrication.

BACKGROUND OF THE INVENTION

Field effect transistors (FETs) that are formed on a bulk substrateutilize a punchthrough stopper to isolate the device from the substrate.In contrast, semiconductor-on-insulator (SOI) FETs utilize an insulatorlayer to provide isolation between the device and the substrate. Boththe SOI devices and the devices formed on a bulk substrate haveadvantages and disadvantages. It is therefore desirable to haveimprovements in field effect transistors that can combine advantages ofboth types, and reduce the disadvantages associated with each type.

SUMMARY OF THE INVENTION

In a first aspect, embodiments of the present invention provide asemiconductor structure comprising: a semiconductor substrate; apunchthrough stopper region formed on the semiconductor substrate; aninsulator region formed on a portion of the punchthrough stopper region;a gate formed on the insulator region; a fin formed over thepunchthrough stopper region, and traversing the gate; and an epitaxialsemiconductor region disposed on the fin and in direct physical contactwith the punchthrough stopper region.

In a second aspect, embodiments of the present invention provide asemiconductor structure comprising: a semiconductor substrate; apunchthrough stopper region formed on the semiconductor substrate; aninsulator region formed on a portion of the punchthrough stopper region;a gate formed on the insulator region; a plurality of fins formed overthe punchthrough stopper region, and traversing the gate, wherein eachfin of the plurality of fins has a width ranging from about 6 nanometersto about 12 nanometers; and an epitaxial semiconductor region disposedon the plurality of fins and in direct physical contact with thepunchthrough stopper region.

In a third aspect, embodiments of the present invention provide a methodof forming a semiconductor structure, comprising: forming a punchthroughstopper region on a semiconductor substrate; forming an insulator layeron the punchthrough stopper region; forming a plurality of fins on theinsulator layer; forming a gate on the insulator layer, such that theplurality of fins traverse the gate; removing the insulator layer fromunder the plurality of fins, while preserving a portion of the insulatorlayer disposed directly underneath the gate; and forming an epitaxialsemiconductor region disposed on the plurality of fins and in directphysical contact with the punchthrough stopper region.

BRIEF DESCRIPTION OF THE DRAWINGS

The structure, operation, and advantages of the present invention willbecome further apparent upon consideration of the following descriptiontaken in conjunction with the accompanying figures (FIGs.). The figuresare intended to be illustrative, not limiting.

Certain elements in some of the figures may be omitted, or illustratednot-to-scale, for illustrative clarity. The cross-sectional views may bein the form of “slices”, or “near-sighted” cross-sectional views,omitting certain background lines which would otherwise be visible in a“true” cross-sectional view, for illustrative clarity.

Often, similar elements may be referred to by similar numbers in variousfigures (FIGs) of the drawing, in which case typically the last twosignificant digits may be the same, the most significant digit being thenumber of the drawing figure (FIG). Furthermore, for clarity, somereference numbers may be omitted in certain drawings.

FIG. 1 shows a semiconductor structure at a starting point forembodiments of the present invention.

FIG. 2 shows a semiconductor structure after a subsequent process stepof performing an anisotropic etch on the insulator region, in accordancewith embodiments of the present invention.

FIG. 3 shows a semiconductor structure after a subsequent process stepof performing an isotropic etch on the insulator region, in accordancewith embodiments of the present invention.

FIG. 4 shows a semiconductor structure after a subsequent process stepof forming an epitaxial region, in accordance with embodiments of thepresent invention.

FIG. 5 is a flowchart indicating process steps for an embodiment of thepresent invention.

DETAILED DESCRIPTION

Embodiments of the present invention provide a fin type field effecttransistor (FinFET) and methods of fabrication. A punchthrough stopperregion is formed on a semiconductor substrate. An insulator layer, suchas silicon oxide, is formed on the punchthrough stopper. Fins and gatesare formed on the insulator layer. The insulator layer is then removedfrom under the fins, exposing the punchthrough stopper. An epitaxialsemiconductor region is grown from the punchthrough stopper to envelopthe fins, while the insulator layer remains under the gate. By growingthe fin merge epitaxial region mainly from the punchthrough stopper,which is part of the semiconductor substrate, it provides a highergrowth rate then when growing from the fins. The higher growth rateprovides better epitaxial quality and dopant distribution. Additionally,an improved strain benefit is also achieved. Another important advantageis that the epitaxial region envelops the fins in the source/drainregion. These advantages result in improved device performance, andreduced variability amongst devices.

FIG. 1 shows a semiconductor structure 100 at a starting point forembodiments of the present invention. A bulk semiconductor substrate 102forms the base of semiconductor structure 100. Bulk substrate 102 may bemade from any of several known semiconductor materials such as, forexample, silicon, germanium, a silicon-germanium alloy, a silicon carbonalloy, a silicon-germanium-carbon alloy, gallium arsenide, indiumarsenide, indium phosphide, III-V compound semiconductor materials,II-VI compound semiconductor materials, organic semiconductor materials,and other compound semiconductor materials. A punchthrough stopperregion (PTS) 104 is formed on the semiconductor substrate 102. The PTS104 is part of the semiconductor substrate that is doped to provideisolation between the substrate 102 and devices formed on the structure100. The type of dopants used depends on the type of devices formed onthe structure. For PFET devices, the dopants in the PTS may include, butare not limited to, arsenic and/or phosphorous. For NFET devices, thedopants in the PTS may include, but are not limited to, boron. The PTSmay be formed by ion implantation, or other suitable method. Aninsulator region 106 is formed on the PTS 104. In embodiments, theinsulator region 106 is comprised of silicon oxide. The insulator region106 has a thickness T1. In embodiments, T1 ranges from about 20nanometers to about 30 nanometers. Fins 108 are formed on the insulatorregion 106. In embodiments, the fins 108 are comprised of silicon,silicon germanium, or other suitable semiconductor material. The finshave a width W1. In embodiments, W1 ranges from about 6 nanometers toabout 12 nanometers. A gate 110 is formed on the insulator region 106.The gate 110 is oriented perpendicular to the fins 108, such that thefins 108 traverse the gate 110. In embodiments, the gate 110 iscomprised of polysilicon. Alternatively, the gate 110 may be a metalgate. The metal gate may be formed using a replacement metal gate (RMG)process. In embodiments, the gate 110 may be comprised of tungsten. Inother embodiments, the gate 110 may be comprised of aluminum. One ormore work function metal layers (not shown) may be part of the gate 110.

FIG. 2 shows a semiconductor structure 200 after a subsequent processstep of performing an anisotropic etch on the insulator region, inaccordance with embodiments of the present invention. As statedpreviously, similar elements may be referred to by similar numbers invarious figures (FIGs) of the drawing, in which case typically the lasttwo significant digits may be the same. For example, bulk substrate 202of FIG. 2 is similar to bulk substrate 102 of FIG. 1. As a result of theanisotropic etch, the insulator region 106 (FIG. 1) is removed from aportion of the PTS 204. A portion of the insulator 206A remains underthe fins 208. A portion of the insulator 206B remains under the gate210.

FIG. 3 shows a semiconductor structure 300 after a subsequent processstep of performing an isotropic etch on the insulator region, inaccordance with embodiments of the present invention. As a result of theisotropic etch, the portion of insulator under the fins 308 is removed,while the portion of insulator layer disposed directly underneath thegate the gate (306) is preserved. The isotropic etch may be a timedetch, such that the semiconductor structure 300 is exposed to theetchant(s) for a sufficient time to remove the insulator under the fins(refer to 206A of FIG. 2), while not significantly effecting theinsulator under the gate (refer to 206B of FIG. 2). The volume of region206A is much smaller than that of region 206B, and thus, a timed etchcan remove the 206A region without significantly effecting the 206Bregion, resulting in structure 300, where the remaining insulator regionis shown as 306. At this point, the fins 308 are mechanically supportedby the gate 310, with no substrate directly below the fins outside ofthe gate 310.

FIG. 4 shows a semiconductor structure 400 after a subsequent processstep of forming an epitaxial region 412, in accordance with embodimentsof the present invention. The epitaxial region 412 is disposed on thefins 408 and in direct physical contact with the punchthrough stopperregion. The epitaxial region envelops the fins. In embodiments, theepitaxial region 412 may comprise silicon. In other embodiments, theepitaxial region 412 may comprise silicon germanium. In embodiments, thesilicon germanium material may be of the form Si(1-x)Ge(x), where x mayrange from about 0.2 to about 0.6. Other ranges are possible and withinthe scope of the present invention. A silicon germanium material may beused with PFETs to provide beneficial stress that enhances carriermobility. PTS 404 has a (100) crystalline surface, facilitating fastergrowth than is possible with a conventional SOI structure, where growthcomes from the fins. In terms of forming the epitaxial region used formerging fins, embodiments of the present invention provide theadvantages of a bulk device. Yet, the gate 410 is isolated fromsubstrate 402 by insulator layer 406, which provides the reduced leakageperformance of a SOI device. Hence, embodiments of the present inventionprovide advantages of both bulk and SOI devices.

FIG. 5 is a flowchart 500 indicating process steps for an embodiment ofthe present invention. In process step 550, a punchthrough stopper isformed. The punchthrough stopper may be formed by implanting dopants inthe semiconductor substrate. In process step 552 an insulator layer isformed. This step maybe performed by forming an oxide such as siliconoxide. The oxide may be formed using a thermal oxidation process, ordeposited using a chemical vapor deposition (CVD) process or othersuitable process. In process step 554 fins are formed on the insulatorlayer. The fins may be formed using a sidewall image transfer (SIT)process or other suitable technique. In process step 556 a gate isformed. The gate may be a polysilicon gate, or alternatively be a metalgate. A replacement metal gate (RMG) technique may be used to form themetal gate. In process step 558, the insulator layer is removed fromunder the fins. This may be accomplished as a two-step etch process.First, an anisotropic etch is performed, resulting in structure 200 ofFIG. 2. Next, an isotropic etch is performed, resulting in structure 300of FIG. 3. The anisotropic etch may be a selective reactive ion etch(RIE). The isotropic etch may be a wet or dry etch that is selective tooxide. In embodiments, the etch time for the isotropic etch may rangebetween about 10 seconds to about 30 seconds. The etch time ispreferably sufficient to remove the regions of insulator under the finswithout significantly removing the insulator from under the gate. Inprocess step 560, an epitaxial semiconductor region is formed on thefins and punchthrough stopper. In embodiments, the epitaxialsemiconductor region is comprised of silicon. In other embodiments, theepitaxial semiconductor region is comprised of silicon germanium. Theepitaxial semiconductor region may also serve to provide beneficialstress/strain to enhance carrier mobility. Note, in embodiments, theorder of the steps may deviate from the order shown. For example, step552 may precede step 550 in some embodiments. Following process step560, industry standard techniques may be used to complete thefabrication of the integrated circuit (IC).

Although the invention has been shown and described with respect to acertain preferred embodiment or embodiments, certain equivalentalterations and modifications will occur to others skilled in the artupon the reading and understanding of this specification and the annexeddrawings. In particular regard to the various functions performed by theabove described components (assemblies, devices, circuits, etc.) theterms (including a reference to a “means”) used to describe suchcomponents are intended to correspond, unless otherwise indicated, toany component which performs the specified function of the describedcomponent (i.e., that is functionally equivalent), even though notstructurally equivalent to the disclosed structure which performs thefunction in the herein illustrated exemplary embodiments of theinvention. In addition, while a particular feature of the invention mayhave been disclosed with respect to only one of several embodiments,such feature may be combined with one or more features of the otherembodiments as may be desired and advantageous for any given orparticular application.

What is claimed is:
 1. A semiconductor structure comprising: asemiconductor substrate; a punchthrough stopper region formed on thesemiconductor substrate; an insulator region formed on a portion of thepunchthrough stopper region; a gate formed on the insulator region; afin formed over the punchthrough stopper region, and traversing thegate; and an epitaxial semiconductor region disposed on the fin, and indirect physical contact with a bottom surface of the fin, and in directphysical contact with the punchthrough stopper region.
 2. Thesemiconductor structure of claim 1, wherein the semiconductor substratecomprises a silicon substrate.
 3. The semiconductor structure of claim1, wherein the punchthrough stopper (PTS) region comprises a dopedregion of the semiconductor substrate and comprises a (100) crystallinesurface.
 4. The semiconductor structure of claim 1, wherein theepitaxial semiconductor region is also in direct physical contact withthe punchthrough stopper region.
 5. The semiconductor structure of claim2, wherein the punchthrough stopper region comprises arsenic dopants. 6.The semiconductor structure of claim 2, wherein the punchthrough stopperregion comprises phosphorous dopants.
 7. The semiconductor structure ofclaim 2, wherein the punchthrough stopper region comprises borondopants.
 8. The semiconductor structure of claim 2, wherein theinsulator region comprises silicon oxide.
 9. The semiconductor structureof claim 8, wherein the insulator region has a thickness ranging fromabout 20 nanometers to about 30 nanometers.
 10. The semiconductorstructure of claim 1, wherein the epitaxial semiconductor regioncomprises silicon.
 11. The semiconductor structure of claim 1, whereinthe epitaxial semiconductor region comprises silicon germanium.
 12. Asemiconductor structure comprising: a semiconductor substrate; apunchthrough stopper region formed on the semiconductor substrate; aninsulator region formed on a portion of the punchthrough stopper region;a gate formed on the insulator region; a plurality of fins formed overthe punchthrough stopper region, and traversing the gate, wherein eachfin of the plurality of fins has a width ranging from about 6 nanometersto about 12 nanometers; and an epitaxial semiconductor region disposedon the plurality of fins, and in direct physical contact with a bottomsurface of each fin, and in direct physical contact with thepunchthrough stopper region.
 13. The semiconductor structure of claim12, wherein the semiconductor substrate comprises a silicon substrate.14. The semiconductor structure of claim 12, wherein the punchthroughstopper (PTS) region comprises a doped region of the semiconductorsubstrate and comprises a (100) crystalline surface.
 15. Thesemiconductor structure of claim 12, wherein the epitaxial semiconductorregion is also in direct physical contact with the punchthrough stopperregion.
 16. The semiconductor structure of claim 13, wherein thepunchthrough stopper region comprises arsenic dopants.
 17. Thesemiconductor structure of claim 13, wherein the punchthrough stopperregion comprises boron dopants.
 18. The semiconductor structure of claim13, wherein the insulator region comprises silicon oxide.
 19. Thesemiconductor structure of claim 13, wherein the epitaxial semiconductorregion comprises silicon.
 20. The semiconductor structure of claim 13,wherein the epitaxial semiconductor region comprises silicon germanium.